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Last updated at 7:44 am UTC on 14 March 2012

Warning: this page expresses strong opinions on this subject. I do not wish to start a flame war. This is a very personal take on the subject, and if it offends you, please feel free to express your own views by building your own tools and sharing with us.

For several years I've been looking for an alternative to the usual Verilog/VHDL sythesize/map/place/route/flash cycle. All I wanted was a simple tool that would let me design circuits from the bottom up, by placing primitives and modules as I please. I don't want C++, I want Forth or assembly, so to speak.
Alas, there is nothing of the kind. My hat is off to the folks who made RapidSmith and served as an inspiration (I wasn't sure I could take on a project of this complexity). Alas, RapidSmith is just an enormous Java framework of dubious value (as is any enormous Java framework, as far as I am concerned) as it did not address any of my concerns.

Why not just use the free (as in rancid beer) Xilinx tools? There are several problems with the traditional approach that were a deal-breaker to me (you may have different considerations):

These are only some of my gripes. I could go on but I will leave it as an exercise for the reader: